View ICL71C03ACPI_2104073.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

3-34 features ? typically less than 2 m v p-p noise (200.00mv full scale, lcl8068) ? accuracy guaranteed to 1 count over entire 20,000 counts (2.0000v full scale) ? guaranteed zero reading for 0v input ? true polarity at zero count for precise null detection ? single reference voltage required ? over-range and under-range signals available for auto-ranging capability ? all outputs ttl compatible ? medium quality reference, 40ppm (typ) on board ? blinking display gives visual indication of over range ? six auxiliary inputs/outputs are available for interfacing to uarts, microprocessors or other complex circuitry ? 5pa input current (typ) (8052a) description the icl8052 or icl8068/lcl71c03 chip pairs with their multiplexed bcd output and digit drivers are ideally suited for the visual display dvm/dpm market. the outstanding 4 1 / 2 digit accuracy, 200.00mv to 2.0000v full scale capabil- ity, auto-zero and auto-polarity combine with true ratiometric operation, almost ideal differential linearity and time-proven dual slope conversion. use of these chip pairs eliminates clock feedthrough problems, and avoids the critical board layout usually required to minimize charge injection. when only 2000 counts of resolution are required, the 71c03 can be wired for 3 1 / 2 digits and give up to 30 readings/sec., making it ideally suited for a wide variety of applications. the icl71c03 is an improved cmos plug-in replacement for the lcl7103 and should be used in all new designs. pinouts ordering information part number temp. range ( o c) package pkg. no. icl8052cpd 0 to 70 14 ld pdip e14.3 lcl8052cdd 0 to 70 14 ld cerdip f14.3 lcl8052acpd 0 to 70 14 ld pdip e14.3 icl8052acdd 0 to 70 14 ld cerdip f14.3 icl8068cdd 0 to 70 14 ld cerdip f14.3 icl8068acdd 0 to 70 14 ld cerdip f14.3 lcl8068acjd 0 to 70 14 ld cerdip f14.3 icl71c03cpl 0 to 70 28 ld pdip e28.6 lcl71c03acpl 0 to 70 28 ld pdip e28.6 icl8052/icl8068 (cerdip, pdip) top view icl71c03 (pdip) top view v- comp out ref cap ref bypass gnd ref out ref supply int out +buff in +int in -int in -buff in buff out v++ 1 2 3 4 5 6 7 14 13 12 11 10 9 8 -1.2v v ref icl8052/ icl8068 v+ 4 1 / 2 / 3 1 / 2 pol run/ hold comp in v- reference ref. cap. 1 ref. cap. 2 analog in analog gnd clock in under-range over-range busy d 2 d 3 d 4 b 8 (msb) b 2 d 5 (msd) str obe a-z in a-z out digital gnd d 1 (lsd) b 4 b 1 (lsb) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 august 1997 icl8052/icl71c03, icl8068/icl71c03 precision 4 1 / 2 digit, a/d converter file number 3081.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999
3-35 functional block diagram figure 1. a2 + - a3 + - integ. comp. a1 + - buffer 14 11 9 int out -int in buf out 10 -buf in -1.2v 2 1 -15v 7 8 +15v 12 +int in 13 icl8052/8068 int. ref. 6 3 +buf in 5 ref out 10k w 1k w 300pf 10 m f comp out comp in 5 16 9 multiplexer counters 20 control logic zero crossing detector 21 22 23 icl71c03 ref az out sw3 1 +5v analog gnd analog input 28 busy 18 str obe 13 under 14 12 clock 2 4 1/2 digit/ 2 6 5 1 4 10 m f (typ) cap 2 ref cap 1 8 7 10 11 10k w 0.1 m f ref 1 m f (typ) 17 az in 6 -15v 15 0.22 m f 10k w 90k w 100k w 4 in run/ hold range over range 3 1/2 digit b 1 b 2 b 3 b 4 latch latch latch latch latch lsd msd seven- segment decoder 3 polarity 19 24 25 26 27 d 5 d 4 d 3 d 2 d 1 icl8052/icl71c03, icl8068/icl71c03
3-36 absolute maximum ratings thermal information icl8052, icl8068 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18v differential input voltage (8068) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30v (8052) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6v input voltage (note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15v output short circuit duration all outputs (note 2). . . . . . . inde?nite icl71c03 power supply voltage (gnd to v+) . . . . . . . . . . . . . . . . . . . . . 6.5v negative supply voltage (gnd to v-). . . . . . . . . . . . . . . . . . . . .-17v analog input voltage (note 3) . . . . . . . . . . . . . . . . . . . . . . . v+ to v- digital input voltage (note 4) . . . . . . . . (gnd - 0.3v) to (v+ + 0.3v) operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 o c to 70 o c thermal resistance (typical, note 5) q ja ( o c/w) q jc ( o c/w) cerdip package . . . . . . . . . . . . . . . . 75 20 14 ld pdip package . . . . . . . . . . . . . . 100 n/a 28 ld pdip package . . . . . . . . . . . . . . 65 n/a maximum storage temperature . . . . . . . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering, 10s) . . . . . . . . . . . . 300 o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. notes: 1. for supply voltages less than 15v, the absolute maximum input voltage is equal to the supply voltage. 2. short circuit may be to ground or either supply. rating applies to 70 o c ambient temperature. 3. input voltages may exceed the supply voltages provided the input current is limited to 100 m a. 4. connecting any digital inputs or outputs to voltages greater then v+ or less than gnd may cause destructive device latchup. f or this reason it is recommended that the power supply to the icl71c03 be established before any inputs from sources not on that supply are applied. 5. q ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?cations parameter symbol test conditions min typ max units clock in, run/ hold, 4 1/2 / 3 1/2 i inl v in = 0 - 0.2 0.6 ma i inh v in = +5v - 0.1 10 m a comp. in current i inl v in = 0 - 0.1 10 m a i inh v in = +5v - 0.1 10 m a threshold voltage v inth - 2.5 - v all outputs v ol i ol = 1.6ma - 0.25 0.40 v b 1 , b 2 , b 4 , b 8 ,d 1 , d 2 , d 3 , d 4 , d 5 v oh i oh = -1ma 2.4 4.2 - v busy, strobe, over-range, under-range polarity v oh i oh = -10 m a 4.9 4.99 - v switches 1, 3, 4, 5, 6 r ds(on) - 400 - w switch 2 r ds(on) - 1200 - w switch leakage (all) i d(off) -2- pa +5v supply range v+ 4 5 6 v -15v supply range v- -5 -15 -18 v +5v supply current i+ f clk = 0 - 1.1 3 ma -15v supply current i- f clk = 0 - 0.8 3 ma power dissipation capacitance c pd vs clock frequency - 40 - pf clock frequency (note 6) dc 2000 1200 khz note: 6. this specification relates to the clock frequency range over which the icl71c03(a) will correctly perform its various functio ns. see the max clock frequency section under component value selection for limitations on the clock frequency range in a system. icl8052/icl71c03, icl8068/icl71c03
3-37 icl8068 electrical speci?cations v supply = 15v, t a = 25 o c, unless otherwise speci?ed parameter symbol test conditions icl8068 icl8068a units min typ max min typ max each operational amplifier input offset voltage v os v cm = 0v - 20 65 - 20 65 mv input current (either input) (note 7) i in v cm = 0v - 175 250 - 80 150 pa common-mode rejection ratio cmrr v cm = 10v 70 90 - 70 90 - db non-linear component of common- mode rejection ratio (note 8) v cm = 2v - 110 - - 110 - db large signal voltage gain a v r l = 50k w 20,000 - - 20,000 - - v/v slew rate sr - 6 - - 6 - v/ m s unity gain bandwidth gbw - 2 - - 2 - mhz output short-circuit current i sc -5- -5-ma comparator amplifier small-signal voltage gain a vol r l = 30k w - - 4000 - - - v/v positive output voltage swing +v o 12 13 - 12 13 - v negative output voltage swing -v o -2.0 -2.6 - -2.0 -2.6 - v voltage reference output voltage v o 1.5 1.75 2.0 1.60 1.75 1.90 v output resistance r o -5- -5- w temperature coefficient tc - 50 - - 40 - ppm/ o c supply voltage (v++ -v-) v supply 10 - 16 10 - 16 v supply current total i supply - - 14 - 8 14 ma icl8052 electrical speci?cations v supply = 15v, t a = 25 o c, unless otherwise speci?ed parameter symbol test conditions icl8052 icl8052a units min typ max min typ max each operational amplifier input offset voltage v os v cm = 0v - 20 75 - 20 75 mv input current (either input) (note 7) i in v cm = 0v - 5 50 - 2 10 pa common-mode rejection ratio cmrr v cm = 10v 70 90 - 70 90 - db non-linear component of common- mode rejection ratio (note 8) v cm = 2v - 110 - - 110 - db large signal voltage gain a v r l = 50k w 20,000 - - 20,000 - - v/v slew rate sr - 6 - - 6 - v/ m s unity gain bandwidth gbw - 1 - - 1 - mhz output short-circuit current i sc -20- -20-ma icl8052/icl71c03, icl8068/icl71c03
3-38 comparator amplifier small-signal voltage gain a vol r l = 30k w - 4000 - - - - v/v positive output voltage swing +v o 12 13 - 12 13 - v negative output voltage swing -v o -2.0 -2.6 - -2.0 -2.6 - v voltage reference output voltage v o 1.5 1.75 2.0 1.60 1.75 1.90 v output resistance r o -5- -5- w temperature coefficient tc - 50 - - 40 - ppm/ o c supply voltage (v++ -v-) v supply 10 - 16 10 - 16 v supply current total i supply - 6 12 - 6 14 ma notes: 7. the input bias currents are junction leakage currents which approximately double for every 10 o c increase in the junction temperature, t j . due to limited production test time, the input bias currents are measured with junctions at ambient temperature. in normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, p d . t j =t a +r q ja p d , where r q ja is the thermal resistance from junction to ambient. a heat sink can be used to reduce temperature rise. 8. this is the only component that causes error in dual-slope converter. system electrical speci?cations: icl8068/icl71c03 v++ = +15v, v+ = +5v, v- = -15v, t a = 25 o c, f clk set for 3 readings/sec. parameter test conditions icl8068a/icl71c03 (note 9) icl8068a/icl71c03 (note 10) units min typ max min typ max zero input reading v in = 0v, full scale = 200mv -000.0 000.0 +000.0 -000.0 000.0 000.0 digital reading ratiometric error (note 11) v in = v ref full scale = 2v 0.999 1.000 1.001 0.9999 1.0000 1.0001 digital reading linearity over full scale (error of reading from best straight line) -2v v in +2v - 0.2 1 - 0.5 1 counts differential linearity (difference between worst case step of adjacent counts and ideal step) -2v v in +2v - 0.01 - - 0.01 - counts rollover error (difference in reading for equal positive & negative voltage near full scale) -v in @ +v in ? 2v - 0.2 1 - 0.5 1 counts noise (p-p value not exceeded 95% of time) v in = 0v, full scale = 200mv -3- -2- m v leakage current at input v in = 0v - 200 300 - 100 200 pa zero reading drift (note 12) v in = 0v, 0 o c t a 50 o c - 1 5 - 0.5 2 m v/ o c scale factor temperature coefficient (note 12) v in = 2v, 0 o c t a 50 o c ext. ref. 0ppm/ o c - 3 15 - 2 5 ppm/ o c icl8052 electrical speci?cations v supply = 15v, t a = 25 o c, unless otherwise speci?ed (continued) parameter symbol test conditions icl8052 icl8052a units min typ max min typ max icl8052/icl71c03, icl8068/icl71c03
3-39 detailed description analog section figure 2 shows the equivalent circuit of the analog section of both the icl71c03/8052 and the icl71c03/8068 in the 3 different phases of operation. if the run/ hold pin is left open or tied to v+, the system will perform conversions at a rate determined by the clock frequency: 40,0002 at 4 1 / 2 digit and 4002 at 3 1 / 2 digit clock periods per cycle (see figure 3 for details of conversion timing). auto-zero phase i (figure 2a) during the auto-zero, the input of the buffer is connected to v ref through switch 2, and switch 3 closes a loop around the integrator and comparator, the purpose of which is to charge the auto-zero capacitor until the integrator output does not change with time. also, switches 1 and 2 recharge the reference capacitor to v ref . input integrate phase ii (figure 2b) during input integrate the auto-zero loop is opened and the analog input is connected to the buffer input through switch 4 and c ref . if the input signal is zero, the buffer, integrator and comparator will see the same voltage that existed in the previous state (auto-zero). thus, the integrator output will not change but will remain stationary during the entire input integrate cycle. if v in is not equal to zero, and unbalanced condition exists compared to the auto zero phase, and the integrator will generate a ramp whose slope is proportional to v in . at the end of this phase, the sign of the ramp is latched into the polarity f/f. deintegrate phase ii (figures 2c and 2d) during the deintegrate phase, the switch drive logic uses the output of the polarity f/f in determining whether to close switch 6 or 5. if the input signal is positive, switch 6 is closed and a voltage which is v ref more negative than during auto-zero is impressed on the buffer input. negative inputs will cause +2(v ref ) to be applied to the buffer input via switch 5. thus, the reference capacitor generates the equivalent of a (+) or (-) reference from the single reference voltage with negligible error. the reference voltage returns the output of the integrator to the zero-crossing point established in phase i. the time, or number of counts, required to do this is proportional to the input voltage. since the deintegrate phase can be twice as long as the input integrate phase, the input voltage required to give a full scale reading is 2v ref . system electrical speci?cations: icl8052/icl71c03 v++ = +15v, v+ = +5v, v- = -15v, t a = 25 o c, f clk set for 3 reading/sec. parameter test conditions icl8068a/icl71c03 (note 9) icl8068a/icl71c03 (note 10) units min typ max min typ max zero input reading v in = 0v, full scale = 2v -0.000 0.000 +0.000 -0.000 0.000 0.000 digital reading ratiometric error (note 11) v in = v ref full scale = 2v 0.999 1.000 1.001 0.9999 1.0000 1.0001 digital reading linearity over full scale (error of reading from best straight line) -2v v in +2v - 0.2 1 - 0.5 1 counts differential linearity (difference between worst case step of adjacent counts and ideal step) -2v v in +2v - 0.01 - - 0.01 - counts rollover error (difference in reading for equal positive & negative voltage near full scale) -v in @ +v in ? 2v - 0.2 1 - 0.5 1 counts noise (peak-to-peak value not exceeded 95% of time) v in = 0v, full scale = 200mv, full scale = 2v -20 50 - - - -30 - - m v leakage current at input v in = 0v - 5 30 - 3 10 pa zero reading drift v in = 0v, 0 o c to 70 o c - 1 5 - 0.5 2 m v/ o c scale factor temperature coefficient v in = 2v, 0 o c to 70 o c, ext. ref. 0ppm/ o c - 3 15 - 2 5 ppm/ o c notes: 9. tested in 3 1 / 2 digit (2,000 count) circuit shown in figure 5, clock frequency 12khz. pin 2 71c03 connected to gnd. 10. tested in 4 1 / 2 digit (20,000 count) circuit shown in figure 5, clock frequency 120khz. pin 2 71c03a open. 11. tested with a low dielectric absorption integrating capacitor. see component selection section. 12. the temperature range can be extended to 70 o c and beyond if the auto-zero and reference capacitors are increased to absorb the high temperature leakage of the 8068. icl8052/icl71c03, icl8068/icl71c03
3-40 figure 2a. phase i auto-zero figure 2b. phase ii integrate input figure 2c. phase iii + deintegrate figure 2d. phase iii - deintegrate figure 2. analog section of either icl8052 or icl8068 with icl71c03 a2 + - a3 + - integrator comparator a1 + - buffer c int 3 r int c az zero crossing detector 2 6 5 1 v ref (+1.000v) c ref 4 c stray v in 1 m f a2 + - a3 + - integrator comparator a1 + - buffer c int 3 r int c az zero crossing detector 2 6 5 1 v ref (+1.000v) c ref 4 c stray v in 1 m f polarity ff a2 + - a3 + - integrator comparator a1 + - buffer c int 3 r int c az zero crossing detector 2 6 5 1 v ref (+1.000v) c ref 4 c stray v in 1 m f polarity ff a2 + - a3 + - integrator comparator a1 + - buffer c int 3 r int c az zero crossing detector 2 6 5 1 v ref (+1.000v) c ref 4 c stray v in 1 m f polarity ff icl8052/icl71c03, icl8068/icl71c03
3-41 zero-crossing flip-flop figure 4 shows the problem that the zero-crossing f/f is designated to solve. the integrator output is approaching the zero-crossing point where the count will be latched and the reading displayed. for a 20,000 count instrument, the ramp is changing approximately 0.50mv per clock pulse (10v max integrator output divided by 20,000 counts). the clock pulse feedthrough superimposed upon this ramp would have to be less than 100mv peak to avoid causing signi?cant errors. the ?ip-?op interrogates the data once every clock pulse after the transients of the previous clock pulse and half-clock pulse have died down. false zero-crossings caused by clock pulses are not recognized. of course, the ?ip-?op delays the true zero-crossing by one count in every instance, and if a correction were not made, the display would always be one count too high. therefore, the counter is disabled for one clock pulse at the beginning of phase 3. this one count delay compensates for the delay of the zero crossing ?ip- ?op, and allows the correct number to be latched into the display. similarly, a one count delay at the beginning of phase 1 gives an overload display of 0000 instead of 0001. no delay occurs during phase 2, so that true ratiometric readings result. detailed description digital section the 71c03 includes several pins which allow it to operate conveniently in more sophisticated systems. these include: 4-1/2 / 3-1/2 (pin 2) when high (or open) the internal counter operates as a full 4 1 / 2 decade counter, with a complete measurement cycle requiring 40,002 counts. when held low, the least signi?cant decade is cleared and the clock is fed directly into the next decade. a measurement cycle now requires only 4,0002 clock pulses. all 5 digit drivers are active in either case, with each digit lasting 200 counts with pin 2 high (4 1 / 2 digit) and 20 counts for pin 2 low (3 1 / 2 digit). run/ hold (pin 4) when high (or open) the a/d will free-run with equally spaced measurement cycles every 40,0002/4,002 clock pulses. if taken low, the converter will continue the full mea- surement cycle that it is doing and then hold this reading as long as pin 4 is held low. a short positive pulse (greater then 300ns) will now initiate a new measurement cycle beginning with up to 10,001/1,001 counts of auto zero. of course if the pulse occurs before the full measurement cycle (40,002/4,002 counts) is completed, it will not be recognized and the converter will simply complete the measurement it is doing. an external indication that full measurement cycle has been completed is that the ?rst str obe pulse (see below) will occur 101/11 counts after the end of this cycle. thus, if run/ hold is low and has been low for at least 101/11 counts, converter is holding and ready to start a new measurement when pulsed high. str obe (pin 18) this is a negative-going output pulse that aids in transferring the bcd data to external latches, uarts or microproces- sors. there are 5 negative-going str obe pulses that occur counts phase i phase ii phase iii 4 1 / 2 digit 10,001 10,000 20,001 3 1 / 2 digit 1,001 1,000 2,001 figure 3. conversion timing polarity detected zero crossing occurs zero crossing detected deint phase iii int phase ii az phase i az integrator output clock internal latch busy output number of counts to zero crossing proportional to v in after zero crossing, analog section will be in autozero configuration figure 4. integrator output near zero-crossing true zero crossing clock pulse feedthrough false zero crossing icl8052/icl71c03, icl8068/icl71c03
3-42 once and only once for each measurement cycle starting 101/11 pulses after the end of the full measurement cycle. digit 5 (msd) goes high at the end of the measurement cycle and stays on for 201/21 counts. in the center of this digit pulse (to avoid race conditions between changing bcd and digit drives) the ?rst str obe pulse goes negative for 1 / 2 clock pulse width. similarly, after digit 5, digit 4 goes high (for 200/20 clock pulses) and 100/10 pulses later the str obe goes negative for the second time. this continues through digit 1 (lsd) when the ?fth and last str obe pulse is sent. the digit drive will continue to scan (unless the previous signal was over-range) but no additional str obe pulses will be sent until a new measurement is available. busy (pin 28) busy goes high at the beginning of signal integrate and stays high until the ?rst clock pulse after zero-crossing (or after end of measurement in the case of an over-range). the internal latches are enabled (i.e., loaded) during the ?rst clock pulse after busy and are latched at the end of this clock pulse. the circuit automatically reverts to auto-zero when not busy so it may also be considered an a-z signal. a very simple means for transmitting the data down a single wire pair from a remote location would be to and busy with clock and subtract 10,001/1,001 counts from the number of pulses received - as mentioned previously there is one no- count pulse in each reference integrate cycle. over-range (pin 4) this pin goes positive when the input signal exceeds the range (20,000/2,000) of the converter. the output f-f is set at the end of busy and is reset to zero at the beginning of reference integrate in the next measurement cycle. under-range (pin 13) this pin goes positive when the reading is 9% of range or less. the output f-f is set at the end of busy (if the new reading is 1800/180 or less) and is reset a the beginning of signal integrate of the next reading. polarity (pin 3) this pin is positive for a positive input signal. it is valid even for a zero reading. in other words, +0000 means the signal is posi- tive but less than the least signi?cant bit. the converter can be used as null detector by forcing equal (+) and (-) readings. the null at this point should be less than 0.1 lsb. this output becomes valid at the beginning of reference integrate and remains correct until it is revalidated for the next measurement. digit drives (pins 19, 24, 25, 26, and 27) each digit drive is a positive-going signal which lasts for 200/20 clock pulses. the scan sequence is d 5 (msd), d 4 , d 3 , d 2 , and d 1 (lsd). all ?ve digits are scanned even when operating in the 3 1 / 2 digit mode, and this scan is continuous unless and over-range occurs. then all digit drives are blanked from the end of the str obe sequence until the beginning of reference integrate, at which time d 5 will start the scan again. this gives a blinking display as a visual indication of over-range. bcd (pins 20, 21, 22 and 23) the binary coded decimal bit b 8 , b 4 , b 2 , and b 1 are positive logic signals that go on simultaneously with the digit driver. figure 5. timing diagram for outputs auto counts 10,001 integrator busy signal counts 10,000 integ. reference counts max 20,001 / 2,001 integrate d 5 d 4 d 3 d 2 d 1 auto zero digit scan for over-range signal integrate reference integrate d 1 d 2 d 3 d 4 d 5 ? first d 5 of az and ref int one count longer str obe 1000 ? /100 counts digit scan for o ver-range expanded scale below / 1,000 over-range when applicable under-range when applicable output / 1,001 zero full measurement cycle 40,002/4,002 counts icl8052/icl71c03, icl8068/icl71c03
3-43 component value selection for optimum performance of the analog section, care must be taken in the selection of values for the integrator capacitor and resistor, auto-zero capacitor, reference voltage, and conversion rate. these values must be chosen to suit the particular application. integrating resistor the integrating resistor is determined by the full scale input voltage and the output current of the buffer used to charge the integrator capacitor. this current should be small compared to the output short circuit current such that thermal effects are kept to a minimum and linearity is not affected. values of 5 m a to 40 m a give good results with a nominal of 20 m a. the exact value may be chosen by: note: if gain is used in the buffer ampli?er, then: integrating capacitor the product of integrating resistor and capacitor is selected to give 9v swing for full scale inputs. this is a compromise between possibly saturating the integrator (at +14v) due to tolerance buildup between the resistor, capacitor and clock and the errors a lower voltage swing could induce due to offsets referred to the output of the comparator. in general, the value of c int is given by: a very important characteristic of the integrating capacitor is that it has low dielectric absorption to prevent roll-over or ratiometric errors. a good test for dielectric absorption is to use the capacitor with the input tied to the reference. this ratiometric condition should be read half scale 1.0000, and any deviation is probably due to dielectric absorption. polypropylene capacitors give undetectable errors at reason- able cost. polystyrene and polycarbonate capacitors may be used in less critical applications. auto-zero and reference capacitor the size of the auto-zero capacitor has some in?uence on the noise of the system, with a larger value capacitor giving less noise. the reference capacitor should be large enough such that stray capacitance to ground from its nodes is negligible. when gain is used in the buffer ampli?er the reference capacitor should be substantially larger than the auto-zero capacitor. as a rule of thumb, the reference capacitor should be approximately the gain times the value of the auto-zero capacitor. the dielectric absorption of the reference cap and auto-zero cap are only important at power-on or when the circuit is recovering from an overload. thus, smaller or cheaper caps can be used here if accurate readings are not required for the ?rst few seconds of recovery. reference voltage the analog input required to generate a full scale output is: v in = 2v ref . the stability of the reference voltage is a major factor in the overall absolute accuracy of the converter. for this reason, it is recommended that an external high quality reference be used where ambient temperature is not controlled or where high-accuracy absolute measurements are being made. buffer gain at the end of the auto-zero interval, the instantaneous noise voltage on the auto-zero capacitor is stored and subtracted from the input voltage while adding to the reference voltage during the next cycle. the result of this is that the noise voltage is effectively somewhat greater than the input noise voltage of the buffer itself during integration. by introducing some voltage gain into the buffer, the effect of the auto-zero noise (referred to the input) can be reduced to the level of the inherent buffer noise. this generally occurs with a buffer gain of between 3 and 10. further increase in buffer gain merely increases the total offset to be handled by the auto- zero loop, and reduces the available buffer and integrator swings, without improving the noise performance of the system. the circuit recommended for doing this with the icl8068/icl71c03 is shown in figure 6. r int full scale voltage (see note) 20 m a ------------------------------------------------------------------------------- = r int buffergain () (full scale voltage) 20 m a ------------------------------------------------------------------------------------------- - = c int 10,000(4-1/2 digit) 1000(3-1/2 digit) clock period 20 m a () integrator output voltage swing ------------------------------------------------------------------------------------------------------------------------ - = figure 6. adding buffer gain to icl8068 a2 + - a3 + - integ. comp. a1 + - buffer 14 11 9 int out -int in buf out 10 -buf in -1.2v 2 -15v 1 -15v 7 8 +15v 12 +int in 13 icl8068 int. ref. 6 3 +buf in 5 ref out 10k w 1k w 300pf comp out 100k w 10-50k to icl7104 icl8052/icl71c03, icl8068/icl71c03
3-44 icl8052 vs icl8068 the icl8052 offers signi?cantly lower input leakage currents than the icl8068, and may be found preferable in systems with high input impedances. however, the icl8068 has substantially lower noise voltage, and is the device of choice for systems where noise is a limiting factor, particularly in low signal level conditions. max clock frequency the maximum conversion rate of most dual-slope a/d converters is limited by frequency response of the compara- tor. the comparator in this circuit is no exception, even though it is entirely npn with an open-loop, gain-bandwidth product of 300mhz. the comparator output follows the inte- grator ramp with a 3 m s delay, and at a clock frequency of 160khz (6 m s period) half of the ?rst reference integrate clock period is lost in delay. this means that the meter reading will change from 0 to 1 with 50 m v input, 1 to 2 with 150 m v, 2 to 3 at 250 m v, etc. this transition at midpoint is considered desirable by most users. however, if the clock frequency is increased appreciably above 160khz, the instrument will ?ash 1 on noise peaks even when the input is shorted. for many dedicated applications where the input signal is always on one polarity, the dealy of the comparator need not be limitation. since the non-linearity and noise do not increase substantially with frequency, clock rates of up to approximately 1mhz may be used. for a ?xed clock frequency, the extra count or counts caused by comparator delay will be a constant and can be subtracted out digitally. the minimum clock frequency is established by leakage on the auto-zero and reference caps. with most devices, measurement cycles as long as 10 seconds give no measur- able leakage error. to achieve maximum rejection of 60hz pickup, the signal integrate cycle should be a multiple of 60hz. oscillator frequencies of 300khz, 200khz, 150khz, 120khz, 100khz, 40khz, 33 1 / 3 khz, etc, should be selected. for 50hz rejection, oscillator frequencies of 250khz, 166 2 / 3 khz, 125khz, 100khz, etc. would be suitable. note that 100khz (2.5 readings/second) will reject both 50hz and 60hz. the clock used should be free from signi?cant phase or frequency jitter. a simple two-gate oscillator and one based on cmos 7555 timer are shown in the applications section. the multiplexed output means that if the display takes significant current from the logic supply, the clock should have good psrr. applications speci?c circuits using the 8068/71c03 8052/71c03 figure 7 shows the complete circuit for a 4 1 / 2 digit ( 200mv full scale) a/d converter with led readout using the internal reference of the 8068/52. if an external reference is used, the reference supply (pin 7) should be connected to ground and the 300pf reference cap deleted. the circuit also shows a typical rc input ?lter. depending on the application, the time-constant of this ?lter can be made faster, slower, or the ?lter deleted completely. the 1 / 2 digit led is driven from the 7-segment decoder, with a zero reading blanked by connecting a d 5 signal to rbi input of the decoder. a voltage translation network is connected between the com- parator output of the 8068/52 and the auto-zero input of the 71c03. the purpose of this network is to assure that, during auto-zero, the output of the comparator is at or near the threshold of the 71c03 logic (+2.5v) while the auto-zero capacitor is being charged to v ref (+100mv for a 200mv instrument). otherwise, even with 0v in, some reference inte- grate period would be required to drive the comparator output to the threshold level. this would show up as an equivalent offset error. once the divider network has been selected, the unit-to-unit variation should contribute less than a tenth of a count error. a second feature is the back-to-back diodes, used to lower the noise. in the normal operating mode they offer a high impedance and long integrating time constant to any noise pulses charging the auto-zero cap. at startup or recov- ery from an overload, their impedance is low to large signals so that the cap can be charged up in one auto-zero cycle. the buffer gain does not have to be set precisely at 10 since the gain is used in both the integrate and deintegrate phase. for scale factors other then 200mv the gain of the buffer should be changed to give a 2v buffer output. for 2.0000v full scale this means unity gain and for 20,000mv (1 m v resolution) a gain of 100 is necessary. not all 8068as can operate properly at a gain of 100 since their offset should be less than 10mv in order to accommodate the auto-zero circuitry. however, for devices selected with less than 10mv offset, the noise perfor- mance is reasonable with approximately 1.5 m v near full scale. on all scales less than 200mv, the voltage translation network should be made adjustable as an offset trim. the auto-zero cap should be 1 m f for all scales and the refer- ence capacitor should be 1 m f times the gain of the buffer ampli?er. at this value if the input leakages of the 8052/8068 are equal, the droop effects will cancel giving zero offset. this is especially important at high temperature. some typical component values are shown in table 1. for 3 1 / 2 digit conversion, use 12khz clock. v++ = +15v, v+ = 5v, v- = -15v clock freq. = 120khz (4 1 / 2 digit) or 12khz (3 1 / 2 digit) table 1. specification valve units full scale v in 20 200 2000 mv buffer gain 100 (see note) 10 1 v/v r int 100 100 100 k w c int 0.22 0.22 0.22 m f c az 1.0 1.0 1.0 m f c ref 10 10 1.0 m f v ref 10 100 1000 mv resolution (4 1 / 2 digit) 1 10 100 m v note: comment on offset limitations above. buffer gain does not improve icl8052 noise performance adequately. rb1 rb2 + () rb2 ----------------------------------- - icl8052/icl71c03, icl8068/icl71c03
3-45 figure 7. icl8052a (8068a)/71c03a 4 1 / 2 digit a/d converter v+ 4 1 / 2 / 3 1 / 2 polarity run/ hold comp in v- reference ref. cap. 1 ref. cap. 2 analog in analog gnd clock in under-range over-range busy d 2 d 3 d 4 (msb) b 8 b 2 (msd) d 5 str obe a-z in a-z out digital gnd (lsd) d 1 b 4 (lsb) b 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v- comp out ref cap ref bypass gnd ref out ref supply int out +buff in +int in -int in -buff in buff out v++ 1 2 3 4 5 6 7 14 13 12 11 10 9 8 10 m f -15v 10k w 0.1 m f +5v signal input clock in 120khz = 3 readings/sec 150 w 150 w 4.7k w icl71c03 icl8068 10k w 90k w a b c d e f g b 1 b 2 b 3 b 4 7447 rbi +5v 47k w 1 2 3 4 5 36 10 10 m f 300 m f -15v 300 1k w +15v 100 0.22 m f 1.0 m f -15v 150 w note: for 3 1 / 2 digit, tie pin 2 low and change clock to 12khz. k w k w k w k w figure 8. icl8052-8068/71c03a plasma display circuit 2.5k w 47k w 5k w +5v pol a g hi voltage buffer di 505 pol d 5 d 4 d 3 d 2 d 1 b 8 b 4 b 2 b 1 71c03a 3k w +5v 0v 0.02 m f 0.02 0.02 m f gates are 7409 0.02 m f 0.02 m f m f 8052a/ 8068a a g v+ prog a rbi bi d dm8880 icl8052/icl71c03, icl8068/icl71c03
3-46 a suitable circuit for driving a plasma-type display is shown in figure 8. the high voltage anode driver buffer is made by dionics. the 3 and gates and caps driving bl are needed for interdigit blanking of multiple-digit display elements, and can be omitted if not needed. the 2k and 3k resistors set the current levels in the display. a similar arrangement can be used with nixie a tubes. nixie a is a registered trademark of burroughs corporation. analog and digital grounds extreme care must be taken to avoid ground loops in the layout of 8068 or 8052/71c03a circuits, especially in high sensitivity circuits. it is most important that return currents from digital loads are not fed into the analog ground line. both of the above circuits have considerable current ?owing in the digital ground returns from drivers, etc. a recommended con- nection sequence for the ground lines is shown in figure 9. other circuits for display applications popular lcd displays can be interfaced to the output of the icl71c03 with suitable display drivers, such as the icm7211a as shown in figure 10. a standard cmos 4000 series lcd driver circuit is used for displaying the 1 / 2 digit, the polarity, and the over-range ?ag. a similar circuit can be used with the icm7212a led driver. of course, another full driver circuit could be ganged to the one shown if required. this would be useful if additional annunciators were needed. figure 10 shows the complete circuit for a 4 1 /2 digit ( 2.000v) a/d, again using the internal reference of the 8052a/8068a. figure 11 shows a more complicated circuit for driving lcd displays. here the data is latched into the icm7211 by the str obe signal and overrange is indicated by blanking the 4 digits. a clock oscillator circuit using the icm7555 cmos timer is shown. some other suitable clock circuits are sug- gested in figures 12 and 13. the 2-gate circuit should use cmos gates to maintain good power supply rejection. a problem sometimes encountered with the 8052/68/71c03 a/d is that of gross over-voltage applied in the input. voltage in excess of 2.000v may cause the integrator output to saturate. when this occurs, the integrator can no longer source (or sink) the current required to hold the summing junction (pin 11) at the voltage stored on the auto zero capacitor. as a result, the voltage across the integrator capacitor decreases suf?ciently to give a false voltage reading. this problem can also show up as large-signal instability on overrange conditions. a simple solution to this problem is to use junction fet transistors across the integrator capacitor to source (or sink) current into the summing junction and prevent the integrator ampli?er from saturating, as shown in figure 14. figure 9. grounding sequence device pin dig gnd icl7104 pin 2 digital logic v in i/p + - filter cap 8068 pin 2 comparator pin 11 icl71c03 an gnd c az v ref buff -in (if used) ref voltage buff out external reference (if used) pin 5 icl8052/68 an gnd +15v -15v +5v supply bypass capacitor(s) board edge analog supply bypass capacitors analog supply return digital supply return icl8052/icl71c03, icl8068/icl71c03
3-47 figure 10. driving lcd displays v+ 41/2 / 31/2 pol r/ h comp in v- ref ref. cap. 1 ref. cap. 2 input analog gnd clock ur or busy d 2 d 3 d 4 b 8 b 2 d 5 str obe a-z in a-z out dig gnd d 1 b 4 b 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 icl71c03 5 bp 31 d 1 32 d 2 33 d 3 34 d 4 30 b 3 29 b 2 28 b 1 27 b 0 35 v- 37 - 40 6 - 26 2, 3, 4 osc 36 v+ 1 +5v backplane 28 segments d 1 - d 4 4 1 / 2 digit lcd display +5v -15v 1 m f 0.1 m f 1 2 3 4 5 6 7 14 13 12 11 10 9 8 icl8052 (a) 8068 (a) 22-100pf optional capacitor +5v 100k w input 300 m f 36k w 300k w -15v -15v 1.0 m f 0.22 m f +15v 100k w 10 m f 5k w 10k w 0v clock in (120khz = 3 readings/sec) 0v 11 10 9 2 6 13 8 7 cd4054a 14 12 5 3 4 15 16 1 +5v 0v analog gnd icm7211a icl8052/icl71c03, icl8068/icl71c03
3-48 figure 11. 4 1 / 2 digit lcd dpm with digit blanking on overrange 1 / 2 cd4030 +5v v+ 4 1 / 2 / 3 1 / 2 pol r/ h comp in v- ref ref. cap. 1 ref. cap. 2 input analog gnd clock ur or busy d 2 d 3 d 4 b 8 b 2 d 5 str obe a-z in a-z out dig gnd d 1 b 4 b 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 icl71c03(a) 5 bp 31 d 1 32 d 2 33 d 3 34 d 4 30 b 3 29 b 2 28 b 1 27 b 0 35 v- 37 - 40 6 - 26 2, 3, 4 osc 36 v+ 1 +5v backplane 1 / 4 cd4030 28 segments d 1 - d 4 4 1 / 2 digit lcd display cd4081 cd4071 cd4071 +5v -15v 1 m f 0.1 m f 1 2 3 4 5 6 7 14 13 12 11 10 9 8 icl8052 (a) 8068 (a) 0v out +5v 1 2 3 4 8 7 6 5 v- v+ reset icm7555 0v +5v 4.7k w 10 to 15k w adjust to f cl = 120khz 300pf 0v 22-100pf optional capacitor +5v 100k w input 300 m f 36k w 300k w -15v -15v 1.0 m f 0.22 m f +15v 100k w 10 m f 5k w 10k w +5v 1 / 4 cd4030 icm7211a 0v analog gnd icl8052/icl71c03, icl8068/icl71c03
3-49 interfacing with uarts and microprocessors figure 15 shows a very simple interface between a free-run- ning 8068/8052/71c03a and a uart. the ?ve str obe pulses start the transmission of the ?ve data words. the digit 5 word is 0000xxxx, digit 4 is 1000xxxx, digit 3 is 0100xxxx, etc. also, the polarity is transmitted indirectly by using it to drive the even parity enable pin (epe). if epe of the receiver is held low, a parity ?ag at the receiver can be decoded as a positive signal, no ?ag as negative. a complex arrangement is shown in figure 14. here the uart can instruct the a/d to begin a measurement sequence by a word on rri. the busy signal resets the data ready reset (drr). again str obe starts the transmit sequence. a quad 2 input multiplexer is used to superimpose polarity, over-range, and under-range onto the d 5 word since in this instance it is known that b 2 = b 4 = b 8 = 0. for correct operation it is important that the uart clock be fast enough that each word is transmitted before the next str obe pulse arrives. parity is locked into the uart at load time but does not change in this connection during an output stream. circuits to interface the 71c03(a) directly with three popular microprocessors are shown in figures 17, 18 and 19. the main differences in the circuits are that the im6100 with its 12-bit word capability can accept polarity, over-range, under- range, 4 bits of bcd and 5 digits simultaneously where the 8080/8048 and the mc6800 groups with 8-bit words need to have polarity, over-range and under-range multiplexed onto the digit 5 word - as in the uart circuits. in each case the microprocessor can instruct the a/d when to begin a mea- surement and when to hold this measurement. application notes figure 12. cmos oscillator figure 13. lm311 oscillator figure 14. gross overvoltage protection circuit r 37.5k w f osc = 0.45/rc c 100pf lm311 - + 1 4 3 2 7 8 56k w 1k w 30k w 16k w 16k w 390pf +5v 0.22 m f a2 + - a3 + - integ. comp. a1 + - buffer 14 11 9 int out -int in buf out 10 -buf in -1.2v 2 1 -15v 7 8 +15v 12 +int in 13 8052a/ int. ref. 6 3 +buf in 5 ref out 300pf comp out 100k 0.22 m f 2n5458 2n5461 s d s d 8068a ref comp to icl71c03 note # description answerfax doc. # an016 selecting a/d converters 9016 an017 the integrating a/d converter 9017 an018 dos and donts of applying a/d converters 9018 an023 low cost digital panel meter designs 9023 an028 build an auto-ranging dmm using the 8052a/7103a a/d converter pair, by larry goff 9028 icl8052/icl71c03, icl8068/icl71c03
3-50 figure 15. simple icl71c03/71c03a to uart interface figure 16. complex icl71c03/7103a to uart interface serial output to receiving uart tro uart im6402/3 tbr tbrl 4 3 2 15678 d 1 d 2 d 3 d 4 b 1 b 2 b 4 b 8 epe str obe run/ hold d 5 pol 71c03/a nc +5v 74c157 select 3a 2a 1a 1b 2b 3b d 1 d 2 d 3 d 4 b 1 b 2 b 4 b 8 str obe run/ hold d 5 71c03/a +5v enable busy tro uart im6402/3 tbr tbrl 4 3 2 1 5678 epe rri drr dr 1y 2y 3y pol over under 10k w 100pf icl8052/icl71c03, icl8068/icl71c03
3-51 figure 17. im6100 to icl71c03a/71c03a interface figure 18. icl71c03 to mc6800, mcs650x interface figure 19. icl71c03 to mcs-48, -80, -85 interface d 4 d 3 d 2 d 1 d 5 str obe run/ hold 71c03/a pol over 1 15 80c95 b 8 b 4 b 2 b 1 1 15 80c95 write 1 sense 1 im6101 read 1 12 im6100 12 7 12 sel 3b 2b 1b 1a 1y 2y 74c157 2a 3a 3y en d 5 under over pol b 8 b 1 d 1 71c03 b 4 b 2 d 4 run/ d 3 d 2 hold str obe pa 4 pa 7 pa 6 pa 5 pa 0 pa 1 pa 2 ca1 ca2 pa 3 mc6820 mc680x or mcs650x sel 3b 2b 1b 1a 1y 2y 74c157 2a 3a 3y en d 5 under over pol b 8 b 1 d 1 71c03 b 4 b 2 d 4 run/ d 3 d 2 hold str obe pa 4 pa 7 pa 6 pa 5 pa 0 pa 1 pa 2 stb a pb0 pa 3 8255 8080, 8085, etc. (mode 1) icl8052/icl71c03, icl8068/icl71c03
3-52 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com icl71c03 with icl8052/8068 integrating a/d converter equations the icl71c03 does not have an internal crystal or rc oscillator. it has a clock input only. integration period integration clock period t clock = 1/f clock 60/50hz rejection criterion t int /t 60hz or t int /t 50hz = integer optimum integration current i int = 20 m a full scale analog input voltage v infs (typ) = 200mv to 2.0v = 2v ref integrate resistor integrate capacitor integrator output voltage v int (typ) = 9v output count note: the 4 1 / 2 digit modes lsd will be output as a zero in the 3 1 / 2 digit mode. output type: 4 nibbles bcd with polarity and over-range. power supply: 15v, +5v v++ = +15v v- = -15v v+ = +5v v ref @ 1.75v if v ref not used, ?oat output pin. auto zero capacitor values 0.01 m f < c az < 1 m f reference capacitor value c ref = (buffer gain) x c az t int 10 000 , f clock --------------------- 4-1/2 digit () = t int 1 000 , f clock --------------------- 3-1/2 digit () = r int buffergain () v infs i int ------------------------------------------------------------ - = c int t int () i int () v int -------------------------------- = v int t int () i int () c int -------------------------------- = count 10 000 , v in v ref --------------- (4-1/2 digit) = count 1 000 , v in v ref --------------- (3-1/2 digit) = figure 20. integrator output auto zero (counts) 30,001 - 10,001 3,001 - 1,001 integrate (fixed count) 10,000 1,000 deintegrate (counts) 1 - 20,001 1 - 2,001 (4 1 / 2 digit) (3 1 / 2 digit) total conversion time (t conv ) t conv = 40,002 * t clock (4 1 / 2 digit mode) t conv = 4,002 * t clock (3 1 / 2 digit mode) (in continuous mode) icl8052/icl71c03, icl8068/icl71c03

▲Up To Search▲

Price & Availability of ICL71C03ACPI

	To Download ICL71C03ACPI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .